AbstractAbstract The main goal of this thesis is to investigate the feasibility of a quadrature radio frequency receiver front-end using a second-order sampling topology in CMOS. Second-order sampling combines subsampling with a non-uniform sampling scheme. This non-uniform sampling scheme comprises of two uniform sampling streams with a small time delay between both streams, which allows the generation of an I and Q channel. The second goal is to determine the performance limiting mechanisms in the analog domain. The knowledge of the perfor- mance limiting mechanisms is used to implement the critical parts of a low power Bluetooth receiver in CMOS and determine the nal performance of such a front-end. It is hoped that new receiver architectures oer new wireless applications, outperform traditional receivers in existing applications or oer additional features. The performance limiting mechanisms are derived to be noise folding, clock jitter and quanti- sation noise. The main limiting eect is the quantisation noise, while the ADC is estimated to consume the most power. However, based on Matlab and Cadence simulations, second-order sampling turns out to be suitable for a RF receiver. A receiver with a subsampling ratio of 12 for each channel meets the requirements of the Bluetooth standard and gives the best overall performance. The implemented receiver has an IIP3 of -12.7, noise gure < 10 dB and a power consumption of 18.4 mW excluding ADC.